Embodiments of the present invention relate generally to vision sensors, systems, and methods that allow for image acquisition and processing and, in various embodiments, to vision sensors with pixel circuits and digital processing elements on a single chip.
Vision sensors are generally used in machine vision systems and other systems for obtaining images of physical scenes and processing the images. Such vision sensors typically include a pixel array with photo sensors that each sample light intensity of a corresponding portion of a scene being imaged. Some vision sensors integrate a pixel array and digital processing elements on a single chip to allow for performing some processing of a captured image within the vision sensor chip. However, there is a need for improved vision sensors and algorithms for image processing.
FIG. 1 illustrates a block diagram of a related art single chip vision sensor 100. The vision sensor 100 includes a pixel array 108, a pixel controller 105, a plurality of analog comparators 107, an analog ramp generator 104, a plurality of analog-to-digital converter (ADC) latches 109, and a digital ramp generator 103. The pixel array 108 includes a plurality of pixel circuits 106 that are arranged in rows and columns. Each pixel circuit 106 comprises a light sensitive element, such as a photodiode or the like, to sample light intensity of a corresponding portion of a scene being imaged, and each pixel circuit 106 is configured to provide an analog pixel signal based on the sampled light intensity.
The pixel controller 105 supplies control signals to the pixel circuits 106 in the pixel array 108 to control an operation of the pixel circuits 106. Pixel circuits 106 that are in a same row of the pixel array 108 may share a common row control signal from the pixel controller 105, and pixel circuits 106 that are in a same column of the pixel array 108 may share a common column readout line to provide output. The pixel controller 105 typically controls the pixel circuits 106 to provide output row by row. The analog pixel signals output from each column of pixel circuits 106 in the pixel array 108 are input to a corresponding analog comparator 107.
Analog-to-digital conversion of the analog pixel signals output from the pixel array 108 is performed using the plurality of analog comparators 107, the analog ramp generator 104, the plurality of ADC latches 109, and the digital ramp generator 103. Analog pixel signals output at each column of the pixel array 108 are compared, in the corresponding analog comparator 107, to a common analog reference level generated by the analog ramp generator 104. The digital ramp generator 103 produces a digital signal that is representative of the analog reference level generated by the analog ramp generator 104. When, on any given column, the analog reference level equals a level of the analog pixel signal, the corresponding analog comparator 107 generates a digital output that causes a corresponding ADC latch 109 to latch a value of the digital signal supplied by the digital ramp generator 103.
The vision sensor 100 further includes a control processor 101, a general purpose memory 102, a plurality of image input registers 110, a plurality of input/output (I/O) registers 111, a plurality of shift registers 112, a plurality of arithmetic logic units (ALUs) 113, a plurality of image memory devices 114, and a plurality of digital image buses 118. Control processor 101 is connected to the general purpose memory 102, from which it obtains programs to execute to control elements of the vision sensor 100. Each ADC latch 109 is connected to a corresponding image input register 110, and each image input register 110 is connected, by output data lines, to a corresponding digital image bus 118.
Each digital image bus 118 may be a serial bus that carries data in bit-serial form. Each digital image bus 118 is connected to a corresponding image input register 110, a corresponding I/O register 111, a corresponding shift register 112, a corresponding ALU 113, and a corresponding image memory device 114. The plurality of I/O registers 111 are each connected to the control processor 101 for inputting data from and outputting data to the control processor 101. The plurality of shift registers 112 are each connected to their immediate neighbors on the left and right, if present. Each ALU 113 is connected to the corresponding digital image bus 118 through a set of corresponding registers, which include at least two data input registers (a and b), and a carry register (c).
Each image input register 110 makes digitized image data available, by way of the corresponding digital image bus 118, to the corresponding I/O register 111, the corresponding shift register 112, the corresponding ALU 113, and the corresponding image memory device 114. In a typical processing operation, image data is buffered in the plurality of image memory devices 114 and processed using the plurality of ALUs 113. The processed image data may then be accessed by the control processor 101 though the plurality of I/O registers 111 for secondary data processing and external communication of the processed image data with external devices.
As a practical matter, the capabilities of the vision sensor 100 favor relatively simple filtering operations that characterize early stages of machine vision processing. When applied to more complex algorithms, the computational efficiency that can be derived from the digital processing elements of the vision sensor 100 is highly restricted by communications between the elements and by the simplistic nature of the arithmetic logic units 113. Therefore, there is a need for improved vision sensors for image processing.